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Open Sustainable Technology

https://github.com/nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++
codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl
Added: over 1 year ago - Last Synced: about 1 year ago - Created: May 19, 2015

  • Relevant topics? true
  • External users? true
  • Open source license? true
  • Active? true
  • Fork? false
  • Main Language: Python
  • Commits: 3006
  • Committers: 12
  • Issues: 39
  • Pull Requests: 3
  • Owner: Nic30
  • Stars: 194
  • Forks: 26
  • Packages: 1
  • Downloads: 97
https://github.com/wyvernsemi/riscv

Open source ISS and logic RISC-V 32 bit project
32-bit c-plus-plus co-simulation cpu-model embedded-systems fpga iss linux processor risc-processor risc-v soft-core verilog
Added: over 1 year ago - Last Synced: about 1 year ago - Created: July 20, 2021

  • Relevant topics? true
  • External users? true
  • Open source license? true
  • Active? true
  • Fork? false
  • Main Language: C++
  • Commits: 149
  • Committers: 2
  • Issues: 1
  • Pull Requests: 0
  • Owner: wyvernSemi
  • Stars: 26
  • Forks: 10
  • Packages: 0
https://github.com/vunit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog
asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl
Added: over 1 year ago - Last Synced: about 1 year ago - Created: November 18, 2014

  • Relevant topics? true
  • External users? true
  • Open source license? true
  • Active? true
  • Fork? false
  • Main Language: VHDL
  • Commits: 1899
  • Committers: 97
  • Issues: 107
  • Pull Requests: 101
  • Owner: VUnit
  • Stars: 692
  • Forks: 250
  • Packages: 1
  • Downloads: 12,216