Projects to review | Open Sustainable Technology

Projects to review 4

https://github.com/nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++
codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl
Added: over 1 year ago - Last Synced: 11 months ago - Created: May 19, 2015

Relevant topics? true
External users? true
Open source license? true
Active? true
Fork? false

Main Language: Python
Commits: 3006
Committers: 12
Issues: 39
Pull Requests: 3

Owner: Nic30
Stars: 194
Forks: 26
Packages: 1
Downloads: 97

https://github.com/gasparka/pyha

Describe, simulate and debug hardware in Python
dsp fixed-point python simulation verification vhdl
Added: over 1 year ago - Last Synced: 11 months ago - Created: October 15, 2016

Relevant topics? true
External users? true
Open source license? true
Active? true
Fork? false

Main Language: Jupyter Notebook
Commits: 1396
Committers: 4
Issues: 0
Pull Requests: 200

Owner: gasparka
Stars: 9
Forks: 1
Packages: 1
Downloads: 47

https://github.com/vunit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog
asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl
Added: over 1 year ago - Last Synced: 11 months ago - Created: November 18, 2014

Relevant topics? true
External users? true
Open source license? true
Active? true
Fork? false

Main Language: VHDL
Commits: 1899
Committers: 97
Issues: 107
Pull Requests: 101

Owner: VUnit
Stars: 692
Forks: 250
Packages: 1
Downloads: 12,216

https://github.com/ghdl/ghdl

VHDL 2008/93/87 simulator
compiler gcc ghdl hacktoberfest hardware llvm simulator testbench vhdl
Added: over 1 year ago - Last Synced: 11 months ago - Created: November 18, 2015

Relevant topics? true
External users? true
Open source license? true
Active? true
Fork? false

Main Language: VHDL
Commits: 9231
Committers: 119
Issues: 312
Pull Requests: 32

Owner: ghdl
Stars: 2194
Forks: 343
Packages: 2
Downloads: 33