https://github.com/wyvernsemi/riscv

Open source ISS and logic RISC-V 32 bit project
https://github.com/wyvernsemi/riscv

Keywords

32-bit c-plus-plus co-simulation cpu-model embedded-systems fpga iss linux processor risc-processor risc-v soft-core verilog

Last synced: 11 months ago
JSON representation

Acceptance Criteria

• Revelant topics? true
• External users? true
• Open source license? true
• Active? true
• Fork? false

👍 0

👎 0

Repository metadata

Open source ISS and logic RISC-V 32 bit project

• Host: GitHub
• URL: https://github.com/wyvernsemi/riscv
• Owner: wyvernSemi
• License: gpl-3.0
• Created: 2021-07-20T06:25:27.000Z (almost 4 years ago)
• Default Branch: main
• Last Pushed: 2024-05-11T08:40:42.000Z (12 months ago)
• Last Synced: 2024-05-11T09:42:35.796Z (12 months ago)
• Topics: 32-bit, c-plus-plus, co-simulation, cpu-model, embedded-systems, fpga, iss, linux, processor, risc-processor, risc-v, soft-core, verilog
• Language: C++
• Homepage:
• Size: 29.3 MB
• Stars: 26
• Watchers: 7
• Forks: 10
• Open Issues: 0
• Releases: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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Owner metadata

• Name: Simon Southwell
• Login: wyvernSemi
• Email:
• Kind: user
• Description: Retired logic, s/w and systems designer, with a background in wireless/cellular and high performance computing. Now developing open-source IP for all to use.
• Website: http://www.anita-simulators.org.uk/wyvernsemi
• Location: Cambridge, United Kingdom
• Twitter: simon_southwell
• Company:
• Icon url: https://avatars.githubusercontent.com/u/21970031?u=bdf22eec1569d7fa64fdbf2689ffb738989aa9d8&v=4
• Repositories: 8
• Last ynced at: 2023-04-05T23:55:33.756Z
• Profile URL: https://github.com/wyvernSemi

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GitHub Events

Total

• Issues event: 2
• Watch event: 27
• Delete event: 1
• Issue comment event: 1
• Push event: 112
• Fork event: 13
• Create event: 7

Last Year

• Create event: 1
• Fork event: 5
• Issue comment event: 1
• Issues event: 2
• Push event: 20
• Watch event: 10

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Committers metadata

Last synced: over 1 year ago

Name	Email	Commits
Simon Southwell	s****n@a****k	145
Simon Southwell	s****l@g****m	4

Committer domains:

• anita-simulators.org.uk: 1

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Issue and Pull Request metadata

Last synced: over 1 year ago

More stats: https://issues.ecosyste.ms/repositories/lookup?url=https://github.com/wyvernsemi/riscv

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Score: 3.9512437185814275