https://github.com/wyvernsemi/riscv
Open source ISS and logic RISC-V 32 bit project
32-bit
c-plus-plus
co-simulation
cpu-model
embedded-systems
fpga
iss
linux
processor
risc-processor
risc-v
soft-core
verilog
Added: over 1 year ago - Last Synced: 11 months ago
- Created: July 20, 2021
- Relevant topics? true
- External users? true
- Open source license? true
- Active? true
- Fork? false
- Main Language: C++
- Commits: 149
- Committers: 2
- Issues: 1
- Pull Requests: 0
- Owner: wyvernSemi
- Stars: 26
- Forks: 10
- Packages: 0
