https://github.com/vunit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog
https://github.com/vunit/vunit

Keywords

asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl

Keywords from Contributors

llvm simulator gcc ghdl vunit eda rtl vivado xilinx build-automation

Last synced: 11 months ago
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Acceptance Criteria

Repository metadata

VUnit is a unit testing framework for VHDL/SystemVerilog


Owner metadata


Committers metadata

Last synced: about 1 year ago

Total Commits: 1,899
Total Committers: 97
Avg Commits per committer: 19.577
Development Distribution Score (DDS): 0.649

Commits in past year: 61
Committers in past year: 12
Avg Commits per committer in past year: 5.083
Development Distribution Score (DDS) in past year: 0.689

Name Email Commits
Olof Kraigher o****r@g****m 667
Lars Asplund l****d@g****m 410
umarcor u****l@e****s 247
eine e****e 66
1138-4EB 1****B 60
Slawomir Siluk s****k@g****l 54
Olof Kraigher o****r@a****m 34
Emanuel Schmid e****d@s****h 29
David Stadelmann d****n@s****h 24
Lukas Vik 1****k 18
Josh Smith j****h@g****m 18
Unai Martinez-Corral 3****r 17
Lars Asplund l****l@v****m 15
Lars Asplund l****d@a****m 12
Andreas Ehliar e****r@i****e 11
Olaf van den Berg o****g@s****m 10
Adam Appleby a****y@h****k 9
Colin Marquardt g****b@m****e 9
Felix Nieuwenhuizen f****x@t****m 7
Jon Klapel k****l@t****m 7
std-max 8****x 6
Nick Gasson n****k@n****k 6
Colby Davis c****s@s****m 6
Christian Haettich f****n@g****m 6
Aaron Hartwig a****7@g****m 6
Daniel Carlsson d****l@v****m 5
Pekka Korpinen p****n@i****i 5
Tristan Gingold t****d@f****r 5
Unai Martinez-Corral u****l@a****m 5
Glen Nicholls d****3@g****m 5
and 67 more...

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Issue and Pull Request metadata

Last synced: 11 months ago

Total issues: 107
Total pull requests: 101
Average time to close issues: 9 months
Average time to close pull requests: 3 months
Total issue authors: 75
Total pull request authors: 42
Average comments per issue: 4.43
Average comments per pull request: 3.18
Merged pull request: 58
Bot issues: 0
Bot pull requests: 0

Past year issues: 43
Past year pull requests: 42
Past year average time to close issues: 24 days
Past year average time to close pull requests: 16 days
Past year issue authors: 30
Past year pull request authors: 24
Past year average comments per issue: 1.58
Past year average comments per pull request: 2.14
Past year merged pull request: 25
Past year bot issues: 0
Past year bot pull requests: 0

More stats: https://issues.ecosyste.ms/repositories/lookup?url=https://github.com/vunit/vunit

Top Issue Authors

  • umarcor (6)
  • nselvara (5)
  • albydnc (4)
  • creiter64 (4)
  • yurivict (3)
  • abaebae (3)
  • asicnet (3)
  • tasgomes (2)
  • ru551n (2)
  • PossenigM (2)
  • oscargus (2)
  • LarsAsplund (2)
  • hcommin (2)
  • GlenNicholls (2)
  • cjmeyer (2)

Top Pull Request Authors

  • LarsAsplund (18)
  • umarcor (17)
  • LukasVik (6)
  • nickg (4)
  • oscargus (4)
  • nicdes (4)
  • std-max (3)
  • abaebae (3)
  • awillenbuecher-xq-tec (2)
  • g0t00 (2)
  • kraigher (2)
  • albydnc (2)
  • crdavis12 (2)
  • eine (2)
  • alexrayne (2)

Top Issue Labels

  • Enhancement (21)
  • Simulator support (12)
  • Builtins (9)
  • SystemVerilog (5)
  • Tool: Questa (5)
  • Parsing (5)
  • Bug (5)
  • Verification Components (5)
  • Breaking change (4)
  • Question (4)
  • Tool: NVC (3)
  • Docs (3)
  • ThirdParty: cocotb (2)
  • Tool: GtkWave (2)
  • Tool: GHDL (2)
  • Tool: Surfer (2)
  • Help wanted (2)
  • CoSim (1)
  • CI (1)
  • Tool Bug (1)
  • Tool: Icarus Verilog (1)
  • Duplicate (1)
  • Tool: RivieraPro (1)
  • Tool: ActiveHDL (1)
  • Tool: Verilator (1)
  • ThirdParty: OSVVM (1)

Top Pull Request Labels

  • Enhancement (54)
  • Docs (16)
  • Simulator support (14)
  • Builtins (12)
  • Breaking change (6)
  • CI (6)
  • Tool: NVC (6)
  • Verification Components (5)
  • ThirdParty: OSVVM (5)
  • Bug (5)
  • Parsing (4)
  • Tool: GHDL (3)
  • SystemVerilog (2)
  • Tool: Questa (2)
  • Needs testing (1)
  • Tool: RivieraPro (1)
  • Tool: GtkWave (1)
  • Tool: Surfer (1)

Package metadata

pypi.org: vunit-hdl

VUnit is an open source unit testing framework for VHDL/SystemVerilog.

  • Homepage: https://github.com/VUnit/vunit
  • Documentation: https://vunit-hdl.readthedocs.io/
  • Licenses: Mozilla Public License 2.0 (MPL 2.0)
  • Latest release: 4.7.0 (published about 2 years ago)
  • Last Synced: 2024-06-10T09:01:40.897Z (11 months ago)
  • Versions: 87
  • Dependent Packages: 4
  • Dependent Repositories: 19
  • Downloads: 12,216 Last month
  • Rankings:
    • Downloads: 2.029%
    • Stargazers count: 2.479%
    • Average: 3.204%
    • Dependent repos count: 3.318%
    • Forks count: 3.414%
    • Dependent packages count: 4.781%
  • Maintainers (2)

Dependencies

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.github/workflows/docs.yml actions
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.github/workflows/push.yml actions
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  • ghdl/setup-ghdl-ci master composite
  • msys2/setup-msys2 v2 composite
requirements.txt pypi
  • colorama *
setup.py pypi
  • colorama *

Score: 20.818131465225076