https://github.com/vunit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
https://github.com/vunit/vunit
Keywords
asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl
Keywords from Contributors
llvm simulator gcc ghdl vunit eda rtl vivado xilinx build-automation
Last synced: 11 months ago
JSON representation
Acceptance Criteria
- Revelant topics? true
- External users? true
- Open source license? true
- Active? true
- Fork? false
Repository metadata
VUnit is a unit testing framework for VHDL/SystemVerilog
- Host: GitHub
- URL: https://github.com/vunit/vunit
- Owner: VUnit
- License: other
- Created: 2014-11-18T20:50:51.000Z (over 10 years ago)
- Default Branch: master
- Last Pushed: 2024-06-10T08:49:59.000Z (11 months ago)
- Last Synced: 2024-06-10T08:54:04.764Z (11 months ago)
- Topics: asic, fpga, systemverilog-hdl, testbench, unit-testing, universal-verification-methodology, verification, verilog-hdl, vhdl
- Language: VHDL
- Homepage: http://vunit.github.io/
- Size: 14.5 MB
- Stars: 692
- Watchers: 52
- Forks: 250
- Open Issues: 234
- Releases: 0
-
Metadata Files:
- Readme: README.md
- Contributing: docs/contributing.rst
- License: LICENSE.rst
Owner metadata
- Name: VUnit
- Login: VUnit
- Email:
- Kind: organization
- Description:
- Website:
- Location:
- Twitter:
- Company:
- Icon url: https://avatars.githubusercontent.com/u/6691399?v=4
- Repositories: 4
- Last ynced at: 2023-02-27T00:35:17.972Z
- Profile URL: https://github.com/VUnit
Committers metadata
Last synced: about 1 year ago
Total Commits: 1,899
Total Committers: 97
Avg Commits per committer: 19.577
Development Distribution Score (DDS): 0.649
Commits in past year: 61
Committers in past year: 12
Avg Commits per committer in past year: 5.083
Development Distribution Score (DDS) in past year: 0.689
Name | Commits | |
---|---|---|
Olof Kraigher | o****r@g****m | 667 |
Lars Asplund | l****d@g****m | 410 |
umarcor | u****l@e****s | 247 |
eine | e****e | 66 |
1138-4EB | 1****B | 60 |
Slawomir Siluk | s****k@g****l | 54 |
Olof Kraigher | o****r@a****m | 34 |
Emanuel Schmid | e****d@s****h | 29 |
David Stadelmann | d****n@s****h | 24 |
Lukas Vik | 1****k | 18 |
Josh Smith | j****h@g****m | 18 |
Unai Martinez-Corral | 3****r | 17 |
Lars Asplund | l****l@v****m | 15 |
Lars Asplund | l****d@a****m | 12 |
Andreas Ehliar | e****r@i****e | 11 |
Olaf van den Berg | o****g@s****m | 10 |
Adam Appleby | a****y@h****k | 9 |
Colin Marquardt | g****b@m****e | 9 |
Felix Nieuwenhuizen | f****x@t****m | 7 |
Jon Klapel | k****l@t****m | 7 |
std-max | 8****x | 6 |
Nick Gasson | n****k@n****k | 6 |
Colby Davis | c****s@s****m | 6 |
Christian Haettich | f****n@g****m | 6 |
Aaron Hartwig | a****7@g****m | 6 |
Daniel Carlsson | d****l@v****m | 5 |
Pekka Korpinen | p****n@i****i | 5 |
Tristan Gingold | t****d@f****r | 5 |
Unai Martinez-Corral | u****l@a****m | 5 |
Glen Nicholls | d****3@g****m | 5 |
and 67 more... |
Committer domains:
- autoliv.com: 4
- veoneer.com: 3
- jhuapl.edu: 2
- scs.ch: 2
- gmx.com: 2
- repodinamica.com.br: 1
- oip.be: 1
- noasic.com: 1
- akribis-sys.com: 1
- synective.se: 1
- af-inventions.de: 1
- reynwar.net: 1
- antmicro.com: 1
- free.fr: 1
- iki.fi: 1
- srcinc.com: 1
- nickg.me.uk: 1
- tethers.com: 1
- tdlrali.com: 1
- marquardt-home.de: 1
- hotmail.co.uk: 1
- siemens.com: 1
- isy.liu.se: 1
- gazeta.pl: 1
- ehu.eus: 1
- ses-sri-srv3.jhuapl.edu: 1
- newayselectronics.com: 1
- nordicneurolab.com: 1
- aes-pc0138.eu.autoliv.int: 1
- matrics.ltd.uk: 1
- gmx.de: 1
- sigasi.com: 1
- mikroprojekt.hr: 1
- goodcleanfun.de: 1
- kulanov.org.ua: 1
- oce.com: 1
- hms.se: 1
- kratosdefense.com: 1
- sanitaseg.it: 1
- space.dtu.dk: 1
- aon.at: 1
- xq-tec.com: 1
- hensoldt.net: 1
- ge.com: 1
- sick.de: 1
- anton-schulte.de: 1
- niemex.de: 1
- hhi-extern.fraunhofer.de: 1
- afconsult.com: 1
Issue and Pull Request metadata
Last synced: 11 months ago
Total issues: 107
Total pull requests: 101
Average time to close issues: 9 months
Average time to close pull requests: 3 months
Total issue authors: 75
Total pull request authors: 42
Average comments per issue: 4.43
Average comments per pull request: 3.18
Merged pull request: 58
Bot issues: 0
Bot pull requests: 0
Past year issues: 43
Past year pull requests: 42
Past year average time to close issues: 24 days
Past year average time to close pull requests: 16 days
Past year issue authors: 30
Past year pull request authors: 24
Past year average comments per issue: 1.58
Past year average comments per pull request: 2.14
Past year merged pull request: 25
Past year bot issues: 0
Past year bot pull requests: 0
Top Issue Authors
- umarcor (6)
- nselvara (5)
- albydnc (4)
- creiter64 (4)
- yurivict (3)
- abaebae (3)
- asicnet (3)
- tasgomes (2)
- ru551n (2)
- PossenigM (2)
- oscargus (2)
- LarsAsplund (2)
- hcommin (2)
- GlenNicholls (2)
- cjmeyer (2)
Top Pull Request Authors
- LarsAsplund (18)
- umarcor (17)
- LukasVik (6)
- nickg (4)
- oscargus (4)
- nicdes (4)
- std-max (3)
- abaebae (3)
- awillenbuecher-xq-tec (2)
- g0t00 (2)
- kraigher (2)
- albydnc (2)
- crdavis12 (2)
- eine (2)
- alexrayne (2)
Top Issue Labels
- Enhancement (21)
- Simulator support (12)
- Builtins (9)
- SystemVerilog (5)
- Tool: Questa (5)
- Parsing (5)
- Bug (5)
- Verification Components (5)
- Breaking change (4)
- Question (4)
- Tool: NVC (3)
- Docs (3)
- ThirdParty: cocotb (2)
- Tool: GtkWave (2)
- Tool: GHDL (2)
- Tool: Surfer (2)
- Help wanted (2)
- CoSim (1)
- CI (1)
- Tool Bug (1)
- Tool: Icarus Verilog (1)
- Duplicate (1)
- Tool: RivieraPro (1)
- Tool: ActiveHDL (1)
- Tool: Verilator (1)
- ThirdParty: OSVVM (1)
Top Pull Request Labels
- Enhancement (54)
- Docs (16)
- Simulator support (14)
- Builtins (12)
- Breaking change (6)
- CI (6)
- Tool: NVC (6)
- Verification Components (5)
- ThirdParty: OSVVM (5)
- Bug (5)
- Parsing (4)
- Tool: GHDL (3)
- SystemVerilog (2)
- Tool: Questa (2)
- Needs testing (1)
- Tool: RivieraPro (1)
- Tool: GtkWave (1)
- Tool: Surfer (1)
Package metadata
- Total packages: 1
-
Total downloads:
- pypi: 12,216 last-month
- Total dependent packages: 4
- Total dependent repositories: 19
- Total versions: 87
- Total maintainers: 2
pypi.org: vunit-hdl
VUnit is an open source unit testing framework for VHDL/SystemVerilog.
- Homepage: https://github.com/VUnit/vunit
- Documentation: https://vunit-hdl.readthedocs.io/
- Licenses: Mozilla Public License 2.0 (MPL 2.0)
- Latest release: 4.7.0 (published about 2 years ago)
- Last Synced: 2024-06-10T09:01:40.897Z (11 months ago)
- Versions: 87
- Dependent Packages: 4
- Dependent Repositories: 19
- Downloads: 12,216 Last month
-
Rankings:
- Downloads: 2.029%
- Stargazers count: 2.479%
- Average: 3.204%
- Dependent repos count: 3.318%
- Forks count: 3.414%
- Dependent packages count: 4.781%
- Maintainers (2)
Dependencies
- actions/checkout v3 composite
- actions/setup-python v4 composite
- actions/upload-artifact v3 composite
- actions/checkout v3 composite
- actions/setup-python v4 composite
- actions/upload-artifact v3 composite
- actions/checkout v3 composite
- docker/login-action v1 composite
- actions/checkout v3 composite
- actions/setup-python v4 composite
- ghdl/setup-ghdl-ci master composite
- msys2/setup-msys2 v2 composite
- colorama *
- colorama *
Score: 20.818131465225076