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Open Sustainable Technology

https://github.com/vunit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog
asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl
Added: over 1 year ago - Last Synced: 11 months ago - Created: November 18, 2014

  • Relevant topics? true
  • External users? true
  • Open source license? true
  • Active? true
  • Fork? false
  • Main Language: VHDL
  • Commits: 1899
  • Committers: 97
  • Issues: 107
  • Pull Requests: 101
  • Owner: VUnit
  • Stars: 692
  • Forks: 250
  • Packages: 1
  • Downloads: 12,216
https://github.com/ghdl/ghdl

VHDL 2008/93/87 simulator
compiler gcc ghdl hacktoberfest hardware llvm simulator testbench vhdl
Added: over 1 year ago - Last Synced: 11 months ago - Created: November 18, 2015

  • Relevant topics? true
  • External users? true
  • Open source license? true
  • Active? true
  • Fork? false
  • Main Language: VHDL
  • Commits: 9231
  • Committers: 119
  • Issues: 312
  • Pull Requests: 32
  • Owner: ghdl
  • Stars: 2194
  • Forks: 343
  • Packages: 2
  • Downloads: 33